// Copyright (C) 1953-2022 NUDT
// Verilog module name - hcp_buffer_output 
// Version: HTP_V1.0
// Created:
//         by - fenglin 
//         at - 9.2022
////////////////////////////////////////////////////////////////////////////
// Description:
//         transmit process of host.
//             -top module.
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module hcp_buffer_output
(
        i_clk               ,
        i_rst_n             ,
        
        iv_desp             ,
        i_desp_wr           ,
        
        ov_pkt_bufid        ,
        o_pkt_bufid_wr      ,
        i_pkt_bufid_ack     , 
        
        ov_pkt_raddr,
        o_pkt_rd,
        i_pkt_raddr_ack,
        
        iv_pkt_data,
        i_pkt_data_wr,
        
        o_pkt_output_pulse,
        o_host_inqueue_discard_pulse,     
        o_fifo_overflow_pulse,       
        
        //o_ts_underflow_error_pulse,
        //o_ts_overflow_error_pulse, 
        
        ov_data,
        o_data_wr   
);

// I/O
// clk & rst
input                  i_clk;   
input                  i_rst_n;
//tsntag & bufid input from host_port
(*MARK_DEBUG="true"*)input       [11:0]     iv_desp             ;
(*MARK_DEBUG="true"*)input                  i_desp_wr           ;
//receive pkt from PCB  
(*MARK_DEBUG="true"*)input       [133:0]    iv_pkt_data;
(*MARK_DEBUG="true"*)input                  i_pkt_data_wr;

(*MARK_DEBUG="true"*)output                 o_pkt_output_pulse;
(*MARK_DEBUG="true"*)output                 o_host_inqueue_discard_pulse; 
(*MARK_DEBUG="true"*)output                 o_fifo_overflow_pulse;
// pkt_bufid to PCB in order to release pkt_bufid
(*MARK_DEBUG="true"*)output     [8:0]       ov_pkt_bufid;
(*MARK_DEBUG="true"*)output                 o_pkt_bufid_wr;
(*MARK_DEBUG="true"*)input                  i_pkt_bufid_ack; 
// read address to PCB in order to read pkt data       
(*MARK_DEBUG="true"*)output     [15:0]      ov_pkt_raddr;
(*MARK_DEBUG="true"*)output                 o_pkt_rd;
(*MARK_DEBUG="true"*)input                  i_pkt_raddr_ack;
// transmit pkt to phy     
(*MARK_DEBUG="true"*)output     [8:0]       ov_data ;
(*MARK_DEBUG="true"*)output                 o_data_wr;

wire       [8:0]       wv_bufid_hqm2htx;
wire                   w_bufid_wr_hqm2htx;
wire                   w_bufid_ready_htx2hqm;

host_output_schedule hcp_output_schedule_inst(
.i_clk                          (i_clk    ),
.i_rst_n                        (i_rst_n  ),

.iv_desp_network                (iv_desp       ),
.i_desp_wr_network              (i_desp_wr     ),

.iv_desp_host                   (12'b0       ),
.i_desp_wr_host                 (1'b0        ),
.o_desp_ack_host                (            ),

.ov_bufid                       (wv_bufid_hqm2htx     ),
.o_bufid_wr                     (w_bufid_wr_hqm2htx   ),
.i_bufid_ready                  (w_bufid_ready_htx2hqm)
);

shared_buffer_output #(.frame_gap(5'd22))hcp_tx_inst(
.i_clk  (i_clk  ),
.i_rst_n(i_rst_n),

.iv_pkt_bufid               (wv_bufid_hqm2htx     ),
.i_pkt_bufid_wr             (w_bufid_wr_hqm2htx   ),
.o_pkt_bufid_ack          (w_bufid_ready_htx2hqm),

.ov_pkt_bufid           (ov_pkt_bufid),
.o_pkt_bufid_wr         (o_pkt_bufid_wr),
.i_pkt_bufid_ack        (i_pkt_bufid_ack),  

.ov_pkt_raddr           (ov_pkt_raddr),
.o_pkt_rd               (o_pkt_rd),
.i_pkt_raddr_ack        (i_pkt_raddr_ack),

.iv_pkt_data            (iv_pkt_data),
.i_pkt_data_wr          (i_pkt_data_wr),

.ov_prc_state     ( ),
.ov_opc_state     ( ),

.ov_data            (ov_data ),
.o_data_wr           (o_data_wr),
.i_data_ready           (1'b1)
);
endmodule